In recent years, in the field of CMOS logic LSI technology, the driving efficiency of the transistor has been improved primarily by decreasing the length (L) of the gate of MOS transistor to realize high speed operation and high integration of the LSI. On the other hand, in order to suppress the increase of gate resistance and the degradation of operating speed of the circuit due to the reduction of the gate length, some processes such as silicide or salicide process, which attempt to reduce the resistance of the gate electrode, have become indispensable on the manufacturing of the device.
In CMOS-LSI using a polysilicon gate having a gate length of 0.5 .mu.m to 0.35 .mu.m, W (tungsten) polycide, Ti (titanium) silicide or Co (Cobalt) silicide has been put in practical use. However, as regards the MOS transistor having a gate length of below 0.25 .mu.m, which is expected for practical use in the future, a technique for reducing the resistance of the gate electrode according to the foregoing W polycide, Ti silicide or Co silicide process has not yet been established.
Presently, as the internal basic cell of the application specific LSI (ASIC) of the CMOS, which is typically represented by the SOG (Sea-Of-Gates), standard cell type LSI or the like, one based on a layout disclosed in Japanese Patent Application Laid-Open No. 59-150446, which is shown in FIG. 1, has generally been adopted.
Referring to FIG. 1, reference numeral 701 denotes a group of P-channel MOS transistors, 702 a group of N-channel MOS transistors, 704 an N-well contact diffusion layer, 705 a P-well contact diffusion layer, 706a, 706b, 706c each a P.sup.+ -type diffusion layer, 707a, 707b, 707c an N.sup.+ -type diffusion layer, 708a, 708b a P-channel MOS gate, 709a, 709b an N-channel MOS gate.
That is, the basic cell of FIG. 1 comprises a group 701 of four P-channel MOS transistors and a group 702 of four N-channel MOS transistors. In the group 701, each two P-channel MOS transistors are connected in series in such a manner as sharing a source or drain area. In the group 702, each two N-channel MOS transistors are connected in series in such a manner as sharing a source or drain area. It is because the two-input NAND or NOR gate can efficiently be arranged that the transistors of the basic cell are laid out with each two of them connected in series sharing the source or drain area.
The gate width (W) of the basic cell is typically determined so that it becomes optimal to the standard load of the random logic. The standard load of the random logic comprises, for example, a fan-out number of 2 and an aluminum interconnection load of 2 mm, which corresponds to about 0.5 pF in terms of capacitance. In consequence, the gate width (W) of the basic cell which is presently put in practical use generally accounts for 10 .mu.m to 20 .mu.m.
FIG. 2A illustrates a layout view of a two-input NAND circuit on the basic cell of FIG. 1, and FIG. 2B is an equivalent circuit diagram of the layout of FIG. 2A.
Referring to FIGS. 2A and 2B, 804 denotes an N-well contact diffusion layer, 805 a P-well contact diffusion layer, 806a, 806b, 806c a P.sup.+ -type diffusion layer, 807a, 807b, 807c an N.sup.+ -type diffusion layer, 808a, 808b a P-channel MOS gate, 809a, 809b an N-channel MOS gate, 810 a power line, 811 a ground line, 812 a first input terminal line, 813 a second input terminal line, 814 an output terminal line, and 815 a contact.
Referring to FIG. 2A, the power supply potential is given from the power line 810 through the contact 815 to the N-well contact diffusion layer 804 and the P.sup.+ -type diffusion layers 806a, 806c, and the ground potential is given from the ground line 811 through the contact 815 to the P-well contact diffusion layer 805 and the N.sup.+ -type diffusion layer 807a.
The P-channel MOS gate 808a and the N-channel MOS gate 809a are connected to each other with the second input terminal line 813, and the P-channel MOS gate 808b and the N-channel MOS gate 809b are connected to each other with the first input terminal line 812, and the P.sup.+ -type diffusion layer 806b and the N.sup.+ -type diffusion layer 807c are connected to each other with an output terminal line 814.
Now, it is supposed that a transistor of the basic cell has a gate length (L) of 0.25 .mu.m, a gate width (W) of 10 .mu.m and a thickness (t.sub.ox) of gate oxide film of 7 .mu.nm. In the transistor of 0.25 .mu.m gate length (L) rule, assuming that the P-channel MOS transistor is of a surface channel type, the P-channel MOS gates 808a, 808b of FIG. 2A can be formed with a P-type polysilicon, and the N-channel MOS gates 809a, 809b of FIG. 2A can be formed with an N-type polysilicon.
Such a structure comprising the P-channel MOS gate of P-type polysilicon and the N-channel MOS gate of N-type polysilicon as in the above is typically called a PN gate structure or a dual gate structure. Accordingly, if the gate resistance (R.sub.g) is calculated with the sheet resistance (.rho..sub.s) of the P-type polysilicon and N-type polysilicon taken as 300 .OMEGA./.quadrature. and 100 .OMEGA./.quadrature. respectively, then the following result is obtained. EQU P-channel MOS gate: R.sub.gp =12 k.OMEGA. EQU N-channel MOS gate: R.sub.gN =4 k.OMEGA.
On the other hand, since the gate capacitance (C.sub.g) via the gate oxide film becomes 12.3 fF, the time constant (.tau..sub.g) of the gate per se becomes as follows: EQU P-channel MOS gate: .tau..sub.gP =R.sub.gP .times.C.sub.g =148 ps EQU N-channel MOS gate: .tau..sub.gN =R.sub.gN .times.C.sub.g =49.2 ps
In the CMOS device having a gate length of 0.25 .mu.m, it is anticipated that the propagation delay time (t.sub.pd) of the inverter circuit when the gate resistance is neglected equals about 60 ps while it is anticipated that the propagation delay time (t.sub.pd) when the foregoing time constant of the gate is taken into account equals about 120 ps. As described above, in the CMOS device of the PN gate structure having a gate length of 0.25 .mu.m or below, the effect exerted on the propagation delay time (t.sub.pd) by the gate resistance cannot be ignored.
In other words, if the PN gate structured CMOS device having the gate length of 0.25 .mu.m or below is made according to the conventional basic cell layout to improve the operational characteristics thereof, a process of the gate silicide, salicide or the like aiming at making the gate resistance smaller becomes indispensable. However, as described above, a silicide technique for reducing the resistance of the polysilicon gate having the gate length of 0.25 .mu.m or below stably with a good yield has not yet been established.
If the gate resistance is taken into account in this manner, then the two-input NAND circuit illustrated in FIG. 2B can be represented by an equivalent circuit as shown in FIG. 2C, in which equivalent gate resistances 816a through 816d are added to the gates.
On the other hand, in order to reduce the gate resistance by the layout technique, it has been proposed to improve the gate configuration. As a conventional gate configuration of the basic cell, there is a cell layout as shown in FIG. 3, which is disclosed in Japanese Patent Application Laid-Open No. 60-47441.
Referring to FIG. 3, 901a, 901b each denote P-channel MOS transistor group, 902a, 902b an N-channel MOS transistor group, 904a, 904b, 904c an N-well contact diffusion layer, 905a, 905b, 905c a P-well contact diffusion layer, 906a, 906b, 906c, 906d, 906e, 906f, 906g a P.sup.+ -type diffusion layer, 907a, 907b, 907c, 907d, 907e, 907f, 907g an N.sup.+ -type diffusion layer, 908a, 908b, 908c, 908d a P-channel MOS gate, 909a, 909b, 909c, 909d an N-channel MOS gate.
That is, the basic cell of FIG. 3 comprises the group 901b of two P-channel MOS transistors connected in series in such a manner as sharing the source or drain area, the group 901a of two P-channel MOS transistors each having the gate electrode extending along the periphery of the source or drain diffusion area, the group 902b of two N-channel MOS transistors connected in series in such a manner as sharing the source or drain area, and the group 902a of two N-channel MOS transistors each having the gate electrode extending along the periphery of the source or drain diffusion area. The basic cell contains eight MOS transistors.
The feature of this coventional basic cell layout lies in that, as shown by 908c, 908d, 909c and 909d of FIG. 3, the gate electrode is made to extend about the source or drain diffusion area. However, this is intended to improve the configuration of the gate electrode aiming at laying out the functional block, in particular the memory cell, efficiently, and not to realize reduction of the resistance of the gate electrode which the present invention intends to achieve.
As described above, in the conventional basic cell structure of the semiconductor integrated circuit, since the gate width of each transistor which constitutes the cell is set aiming at driving the standard load, if a similar cell layout is used for a CMOS device having a gate length of 0.25 .mu.m or below, then the gate resistance is increased, and the operating speed of the circuit is reduced.
Further, in order to reduce the gate resistance by using a specific manufacturing process, the number of manufacturing step has been increased as in the silicide or salicide process or the like.